This invention relates to high-slew-rate operational amplifiers (called op amps) that find suitable applications in sample-and-hold circuits and switched-capacitor filters.
FIG. 18 shows an inverting amplifier using a conventional op amp of the two-stage configuration. FIG. 18 shows a case in which two NMOS transistors act as a differential-input-stage transistor pair (called a differential pair).
As shown in FIG. 18, the first stage is a differential amplifier that is made up of a differential input stage and an active load. The differential input stage is formed by NMOS transistors Q1, Q2 and an NMOS transistor Q8 acting as a constant-current source. These transistors Q1 and Q2 are connected together source-to-source. The active load is formed by PMOS transistors Q4 and Q5. On the other hand, the second stage is an inverter amplifier formed by a common-source PMOS transistor Q7 and an NMOS transistor Q6 acting as an active load. Cc is a compensation capacitor for phase compensation. CL is a load capacitor. R is a resistor. Since the gain of op amps is very high, this usually requires application of negative feedback.
In the above-described conventional op amp, the slew rate is determined by Io (i.e., the bias current of the first-stage differential amplifier) or Is (i.e., the bias current of the constant-current source load of the second-stage inverter amplifier), when inputting large signals. FIG. 18 illustrates this situation. In a steady state in which a virtual short holds, an electric current flowing in each of Q1 and Q2 is Io/2. Under this condition, if the input voltage V.sub.in rises rapidly up to V.sub.1, the output voltage V.sub.out tries to go down to -V.sub.1. However, the output voltage V.sub.out cannot catch up with such a sudden rise in the input voltage V.sub.in, as a result of which the potential of the gate of Q2 goes up and Q1 is cut off. Therefore, the current Io comes to flow in Q2. The current Io is mirrored to Q4 by the active load comprising Q4 and Q5. This current Io will try to charge the compensation capacitor Cc at a rate Sr1 given by the following formula (1): EQU Sr1=dV/dt=Io/Cc (1)
Io: 1st-stage differential amplifier's bias current PA1 Cc: compensation capacitor's capacitance PA1 Is: 2nd-stage inverter amplifier's bias current PA1 CL: load capacitor's capacitance PA1 gm: Q1's transconductance PA1 g1: Q1's output conductance PA1 g2: Q4's output conductance PA1 a differential input stage having first and second transistors of the first conductivity type that are connected together source-to-source and a constant-current source that is connected with sources of the first and second transistors; PA1 third, fourth, and fifth transistors of the second conductivity type that are connected together source-to-source; PA1 a bias feed means for feeding a bias current to sources of the third, fourth, and fifth transistors; and PA1 a current mirror circuit that has a plurality of transistors of the first conductivity type; PA1 wherein: PA1 a noninverting input voltage is applied to a gate of the third transistor, and an inverting input voltage is applied to a gate of the fourth transistor, and a source voltage of the first and second transistors is applied to a gate of the fifth transistor; and PA1 a differential input stage having first and second transistors of the first conductivity type that are connected together source-to-source and a constant-current source that is connected with sources of the first and second transistors; PA1 a third transistor of the first conductivity type and a fourth transistor of the second conductivity type, the third and fourth transistors being connected together source-to-source; PA1 a fifth transistor of the second conductivity type and a sixth transistor of the first conductivity type, the fifth and sixth transistors being connected together source-to-source; PA1 a current mirror circuit that has a plurality of transistors of the first conductivity type; PA1 wherein:
Meanwhile, the output voltage V.sub.out tries to go down to -V.sub.1 at a rate Sr2 given by the following formula (2): EQU Sr2=dV/dt=(Is-Io)/CL (2)
The output slew rate is determined by Sr1 or Sr2, whichever is lower. Because of this fact, it is necessary to increase both Sr1 and Sr2 by increasing both Io and Is for enhancing the slew rate.
However, for the conventional op amp, it is not that easy, since the increase in the bias current not only dissipates much more power but also results in the degradation of the small-signal properties of the differential amplifier. Therefore, the conventional technique finds hard to increase the slew rate. In the differential amplifier the small-signal voltage gain, Av, is given by the following formula (3). g1 and g2 increase in proportion to the current and gm increases in proportion to the square root of the current. This means that the small-signal voltage gain Av decreases as the current increases. EQU Av=gm/(g1+g2) (3)
M. G. Degrauwe et al try to provide a solution to the above-identified problem in their work entitled "Adaptive Biasing CMOS Amplifiers," IEEE Journal of Solid-State Circuits, Vol. SC-17, No. 3, June 1982, pp. 522-528. This paper considers an op amp shown in FIG. 19 for OTA (Operational Transconductance Amplifier). The operation of the FIG. 19 op amp is described below. Q11 to Q31 are transistors. The differential input stage consists of Q11 and Q12, connected together source-to-source, and Q13 acting as a constant-current source. The transistors Q21, Q23, Q24, and Q25 jointly constitute a difference current amplifier circuit. The transistor Q25 turns off if I20&gt;I22 where I20 is the current flowing in Q20 and I22 is the current flowing in Q22. On the other hand, if I20&lt;I22, this turns the transistor Q25 on, thereby allowing a current of M.times.(I22-I20) to flow, where M is the mirror ratio of a current mirror circuit formed by Q24 and Q25. Likewise, the transistors Q27, Q29, Q30, and Q31 jointly constitute another difference current amplifier circuit. If I28&gt;I26 where I28 is the current flowing in Q28 and I26 is the current flowing in Q26, then an M.times.(I28-I26) current flows in Q31. At this point in time, I16 (i.e., the current flowing in Q16) is mirrored to I20 and I28, and I17 (i.e., the current flowing in Q17) has been mirrored to I22 and I26. As a result, in a steady state where I16=I17 holds, a given bias current through Q13 flows. If a difference is produced between the currents I16 and I17, then a current proportional to that difference is added to the bias current in order to improve the slew rate.
However, the above-described op amp presents the problem that the current I16 flows into Q20 and Q28 and the current I17 flows into Q22 and Q26. This considerably dissipates power. Further, much larger circuitry is required.
Another solution is offered by R. Klinke et al. in a paper entitled "A Very-High-Slew-Rate CMOS Operational Amplifier," IEEE Journal of Solid-State Circuits, Vol. 24, No. 3, June 1989, pp. 744-746. This paper considers an op amp shown in FIG. 20. In the aforesaid solution proposed by M. G. Degrauwe et al, a Current proportional to a difference between specified two currents is added to a bias current. In this solution offered by R. Klinke et al., biasing is controlled according to the difference in voltage between inputs. In FIG. 20, Q41 to Q56 are transistors. The differential input stage is made up of Q41 and Q42, connected together source-to-source, and Q43 acting as a constant-current source. Here, the sizes of Q52, Q53, and Q54 are designed such that both nodes D an E are held LOW when the gate voltages of Q50 and Q51 are identical. As a result of such an arrangement, in the steady state both Q55 and Q56 are cut off and the differential input stage is biased by a given current through Q43. Now suppose that a great difference in voltage is produced between V.sub.in+ (i.e., the noninverting input voltage) and V.sub.in- (i.e., the inverting input voltage). If V.sub.in+ &gt;V.sub.in-, the node E goes HIGH thereby turning Q56 on and a current flowing in Q56 is added to the bias current. On the other hand, if V.sub.in- &gt;V.sub.in+, this causes Q55 to turn on. In comparison with the solution by M. G. Degrauwe et al, the circuit size can be held smaller and the power consumption can be held low by this solution.
However, the op amp proposed by R. Klinke et al., too, suffers from the following problem. The nodes D and E are high-impedance nodes, so that both the transistors Q55 and Q56 undergo a sudden turn-off or turn-on. As a result, the sudden increase or decrease in the bias current occurs. This not only degrades the settling characteristics but also generates unwanted noise.